Device-deviation tolerant over-1 GHz clock distribution scheme with skew-immune race-free impulse latch circuits

Clock skew (and jitter) is becoming the major obstacle to high-frequency clock distribution in sub-quarter micron CMOS LSIs, because skew cannot be scaled down even by use of scaled devices and may significantly increase as a result of device and operating environment deviations. To overcome this obstacle, the authors present skew-immune race-free impulse latch circuits and a reduced-skew ring-type clocking scheme. The 1 GHz clock test chip is integrated into a 6/spl times/6 mm/sup 2/ die with 0.18 /spl mu/m CMOS and double-layer-metal technology. The supply voltage is 1.8 V. The threshold voltage of the nMOS transistors is about 0.3 V and that of the pMOS transistors is about -0.3 V. 1 GHz global clock distribution shows less than 50 ps clock skew for those points on the chip.