An algorithm for generating circuit diagrams of LSIs

The degree of IC integration has shown yearly increases. Hence, the amount of layout data also has increased. Therefore it is very important to verify that a given circuit is realized correctly on a layout. To simplify verification we reconstruct the diagram of a given circuit from its layout data. We present an algorithm for reconstruction and describe a system which incorporates it. The circuit diagrams reconstructed by this algorithm resemble these drawn by layout designers. Hence it is a very effective means of layout verification. In this algorithm we use a graph to show the interconnections of transistors given by layout data. We group transistors into a number of subgroups so that each group forms a logical unit. Then we determine the positions of the transistors within each group and the positions of the logical units. Finally we reconstruct a circuit diagram resembling the hand drawn one by determining the final positions of the transistors of the circuit based on those positions.