Digital correction of circuit imperfections in cascaded /spl Sigma/-/spl Delta/ modulators composed of 1st-order sections

An approach to remove the effects of amplifier finite gain and C-ratio mismatches in the 1-1-1 (MASH) and the 1-1-1-1 cascaded sigma-delta modulator is presented. By correcting the digital outputs with estimates of the parasitic errors due to analog circuit imperfections, uncancelled quantization noise terms can be removed. A 1-1-1-1 cascaded modulator, implemented as a fully differential switched-capacitor circuit, has been fabricated in a 1.2 /spl mu/m, double-poly, n-well CMOS process. Measurements of the modulator verify that for an amplifier gain of 60 dB, C-ratio mismatch errors of 0.52% and 0.054%, the error correction offers an overall improvement in SNDR of 12-22 dB. A 12 /spl mu/V/sub rms/ sine wave can be restored with a positive SNDR.