Improvement in drain-induced-barrier-lowering and on-state current characteristics of bulk Si fin field-effect-transistors using high temperature Phosphorus extension ion implantation

Abstract In this paper, high temperature Phosphorus ion implantation is applied to p-type Si (1 0 0) substrates and n-type bulk Si fin field-effect-transistors. Phosphorus profiles and sheet resistance on p-type Si (1 0 0) substrates are analyzed. High temperature ion implantation shows less Phosphorus diffusion after rapid thermal annealing compared to room temperature ion implantation. In n-type bulk Si fin field-effect-transistors with wide spacers and ion implanted source and drain, the high temperature extension ion implantation shows better electrical characteristics in terms of drain-induced-barrier-lowering, on-state resistance, on-state current, and off-state current. In n-type bulk Si fin field-effect-transistors with narrow spacers and Phosphorus in-situ doped Si epi source and drain, drain-induced-barrier-lowering and off-state current characteristics are improved by high temperature extension ion implantation, compared to room temperature extension ion implantation. Phosphorus distribution in fin field-effect-transistors is analyzed by scanning spreading resistance microscopy. Suppression of Phosphorus diffusion into the channel area is confirmed.