Non-planar III-N transistors with compositional graded semiconductor channels

A III-N semiconductor channel is compositionally graded between a transition layer and a III-N-polarizing layer. In embodiments, a gate stack on side walls of a fin is deposited, which has the graded III-N semiconductor channel, which enables formation of a transport channel in the III-N semiconductor channel adjacent to at least both side wall surfaces in response to a gate bias. In embodiments, a gate stack is deposited completely around a nanowire around comprising a III-N semiconductor channel, which is graded compositionally to the formation of a transport channel in the III-N semiconductor channel adjacent to both of the polarization layer and adjacent to the transition layer in response to a to enable gate bias.