A 7ns/850mW GaAs 4Kb SRAM Fully Operative at 75OC

PROBLEMS AT HIGH TEMPERATURE This paper describes a GaAs 1K x 4b SRAM which has been designed using a novel circuit technology to reduce the scattering and the temperature dependence of the access time. The source-follower circuits were adopted to get a low level voltage enough to make the enhancement FETs off in the next stages. To reduce the subthreshold leakage current in the access transistors of the unselected memory cells, the baselines connected to the unselected memory cells were raised from GND level. The 4Kb SRAM was fabricated using 1.Opm selfaligned MESFETs with buried p-layers beneath the FET regions. The maximum address access time of 7ns and the power dissipation of 850mW were obtained for the galloping test pattern at 75OC. Little change in the address access time was observed over 0 to 75OC.