An ASIC architecture for implementing low-level communication circuits

A flexible architecture model is presented to implement low-layer protocols into silicon. This model is especially well adapted to real-time features (as in industrial and control-command LANs) and provides a significant increase in the message processing speed. The goal is to propose a systematic approach to the problem of communication protocol implementation in hardware: the design methodology presented can lead to architecture synthesis starting from a behavioral description of the protocol in a dedicated language. >