A switched-capacitor Hadamard filter bank in 0.35 /spl mu/m CMOS

This paper describes the design of filter banks that implement analog Hadamard transformers suitable to CMOS technology. A switched-capacitor (SC) topology is employed, including finite-gain and offset compensation techniques to allow the use of low-gain high-bandwidth amplifiers, thereby enabling signal processing by the filter bank at high data rates. The structure may be used as an analysis stage in what has been termed a hybrid filter bank, where post digital signal processing stage can be incorporated to improve A/D conversion accuracy and speed, or in digital communication systems to reduce transmission data rates. Design details, as well as simulation results for a 0.35 mum CMOS manufacturing process are presented, verifying the effectiveness of the proposed scheme