Electrically Testing Non-underfilled Flip Chip Assemblies-Impacts on Interconnect Integrity

The trend towards multi-die flip chip packaging favors the incorporation of a qualified manufacturingcompatible rework process to remove and replace individual defective die. Inherent to the rework process is an electrical verification step that effectively identifies the defective device without compromising the integrity of an otherwise perfectly functional device. Unfortunately, the very feature that optimizes device integrity, that is the underfill, renders subsequent device removal extremely difficult. It is therefore desirable to investigate the behavior of various non-underfilled dies that are subjected to anticipated electrical verification conditions in order to determine whether a safe 'testing window' exists for ensuring product quality and reliability, especially considering that limited information has been published with regards to what compressive loads a non-underfilled bare die can support. This paper presents a comprehensive study of how flip chip (100 micron diameter on 186 micron pitch), Pb-free SAC alloy interconnects behave under compressive loads applied directly to bare die that have been assembled onto an organic substrate without underfill in a multi-chip module (MCM) configuration. For various die sizes, a series of loads were examined in order to cover a vast range of possible forces used to ensure electrical contact to non-planar organic packages. Loads were applied at both ambient and elevated temperature and at both a normal angle and an artificially tilted angle. Characterizations by load-curve analysis, co-planarity and interconnect height measurements as well as X-ray tomography demonstrated that normal angle loading induced a limited degree of deformation (