Hole current shunting type power transistor with high avalanche tolerance and preparation method thereof

The invention discloses a hole current shunting type power transistor with high avalanche tolerance and a preparation method thereof. The hole current shunting type power transistor is characterized in that an N-type silicon-doped epitaxial layer is arranged on an N-type silicon-doped substrate serving as a drain region, grooves are formed in the surface of the N-type silicon-doped epitaxial layer, a field oxide layer is arranged in each groove, a shield grid and grid electrodes are arranged in each field oxide layer, the grid electrodes are positioned on two sides of the corresponding shield grid and are positioned on the top of the corresponding field oxide layer, and insulated dielectric layers are arranged between each shield grid and the corresponding gird electrodes; meanwhile, gate oxide layers are arranged between the grid electrodes and the epitaxial layer, the surface of the epitaxial layer is provided with a P-type body region, the surface of the P-type body region is provided with a P-type source region and an N-type source region, the surface of the device is covered with an insulated dielectric layer, a source electrode metal is in contact with a heavily-doped N-type source region and a heavily-doped P-type source region through through holes in the insulated dielectric layer, the shield grid is further in contact with the source electrode metal, P-type polycrystalline silicon conducting channels positioned under the corresponding grid electrodes are arranged in each field oxide layer, one end of each P-type polycrystalline silicon conducting channel is connected to the N-type silicon-doped epitaxial layer, and the other ends of the P-type polycrystalline silicon conducting channels are connected to the corresponding shield grid.