Realization of Digital Noise Emulator for Characterization of Systems Exposed to Substrate Noise

Frequency and timing of digital clocks, digital switching activities, and number of transistors in digital blocks are the key behavior-level parameters to model switching noise generated by complicated digital systems. In this paper, a Digital Noise Emulator (DNE) is implemented on a test chip to study how these parameters impact the performance of a ring-typed-VCO-based PLL. In addition, the proposed DNE can be used for noise cancellation to improve PLL performance in the presence of deterministic noise.