Low Power Clocking Strategies in Deep

Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (Applied Specific Integrated Circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related to clocking strategies and timing closure that were encountered during the design of a FEC40 ASIC, and a methodology is proposed to mitigate some of these issues. The FEC40 ASIC is a Forward Error Correction Chip designed for Nortel's 40Gb/s coherent optical transmission system. The chip has about 11 million gates at a core frequency of 350MHz and has 70 clock domains. The chip was fabricated in a 90nm technology.