6.8 A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS

Baud-rate clock-and-data recovery circuits (CDR) are ubiquitous in recent receiver designs as a means of lowering power consumption by sampling the data only once per UI. To further reduce power, prior works in pattern-based baud-rate PD [1] and FD [2] combine clock & data recovery by sharing comparators between the DFE and the PD. However, both CDRs [1, 2] were manually tuned by sweeping the equalization settings of the CTLE and the comparator levels in order to achieve lock. Since the two settings are correlated, it is time-consuming and tedious to sweep the entire solution space. In this paper, we propose an adaptive engine where the CDR system searches and converges to an optimal lock and sampling point. The proposed scheme, implemented in 28nm CMOS and operating at 36Gb/s, relies on the data eye to autonomously adapt the parameters of a CTLE, a 1-tap DFE, and the PD locking point.