Comparing code coverage metrics for analog behavioral models

In current applications Analog/Mixed-Signal (AMS) circuits gets increasingly demanding. To speed up the design process parts of the design were implemented in hardware description languages. Besides positive aspects like simulation processing times these models need to be checked in terms of verification run set completeness, i.e. input stimuli, parameter setting, and test bench circuitry. For this purposes we present a methodology to adopt code coverage metrics on Verilog-A models. A public domain analog circuit simulator automatically instruments and executes the behavioral description. The coverage results are automatically annotated and compared to a coverage metric based on the reachable analog state-space of the circuit. We discuss the methodology on several examples and sketch a path to improve the completeness of a verification run set.