A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC

A 100MS/s 12-bit SAR ADC designed for terahertz imaging sensor is presented. The proposed ADC utilizes coarse-fine SAR architecture to relax reference requirement and improve operation rate. Split-CDAC structure is applied to reduce chip area, and its LSBs capacitors are reused as a coarse DAC. Redundant capacitor arrays are applied in both coarse and fine ADCs. A power-and-area-efficient ADC with high sampling rate can be realized with these techniques combined. The prototype is implemented in TSMC 1P9M 65nm-CMOS process. The simulation result with noise and other on board non-ideal effects shows that the ADC consumes 1.8 mW with an SNDR 65.7 dB and an SFDR of 77.0 dB with a Nyquist input at 1.2V power supply, achieving an ENOB of 10.6-bit and a FoM of 11.6 fJ/conv-step.