Demonstration of Fine Pitch RDL in Fanout Panel Level Packaging

The fan out panel level package (FOPLP) has been getting significant attention due to its merit of high I/O density by utilizing fan out area, higher productivity thereby low cost by large form factor, and high-degree heterogeneous integration capability. FOPLP was first adapted in a wearable device and is trying to extend its area such as application processor for smartphone, interposer, chip-lets, and so on. For the chip-lets and interposer of high-end substrate, fine pitch redistribution layer (RDL) is of primary importance. In this paper, capabilities of fine pitch RDL in chip first platform and chip last platform were investigated and compared in point of unit topology, depth of focus margin during exposure process, and perspective of mass production. Under the same conditions of photoresist and photolithographic equipment, the surface flatness of chip last platform was 25 percent of that of chip first platform, which gives wide depth of focus margin even at exposure device with numerical aperture of 0.1∼0.16. For the chip last process, the yield and critical dimension of RDL after seed metal etching was measured for the checking homogeneity of RDL over an entire panel. The chip last product is more advantageous than the chip first products for demonstrating fine pitch RDL. The chip last platform with low numerical aperture of 0.1 has a wide range of focus margin and as a result, fine pitch RDL of 3/3 microns is expected to have mass-production capability.