Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators

The open-source hardware/software framework TaPaSCo aims to make reconfigurable computing on FPGAs more accessible to non-experts. To this end, it provides an easily usable task-based programming abstraction, and combines this with powerful tool support to automatically implement the individual hardware accelerators and integrate them into usable system-on-chips. Currently, TaPaSCo relies on the host to manage task parallelism and perform the actual task launches. However, for more expressive parallel programming patterns, such as pipelines of task farms, the round trips from the hardware accelerators back to the host for launching child tasks, especially when exploiting data-dependent execution times, quickly add up. The major contribution of this work is the addition of on-chip task scheduling and launching capabilities to TaPaSCo. This enables not only low-latency dynamic task parallelism, it also encompasses the efficient on-chip exchange of parameter values and task results between parent and child accelerator tasks. Our solution is able to handle recursive task structures and is shown to have latency reductions of over 35x compared to the prior approaches.