Ultra low power comparator for stabilized output

The paper presents a modified dynamic comparator suitable for successive approximation register (SAR) analog-to-digital converter. Improvisations incorporated in the circuit ensure the ultra low power operation of the comparator, maintaining all beneficial attributes of its predecessors. Additional advantages of this circuit are the reduction in the response time of the comparator and die area. The performance of the modified comparator is ensured by the design and simulation using 0.18µm technology in Cadence Virtuoso suit. The results shows power consumption of 142pW at clock frequency of 0.1MHz and 1.5V supply.