Investigation of Hysteresis Phenomenon in Floating-Gate NAND Flash Memory Cells

The origin of hysteresis phenomenon in floating-gate (FG) NAND flash memory cells in cell strings was identified. To analyze the hysteresis phenomenon in FG NAND flash memory strings, pulsed $I$ – $V$ and fast transient bitline current ( $I_{\textrm {BL}}$ ) measurements were used in this study. It was found that the hysteresis phenomenon is originated by traps in the bottom oxide of the oxide/nitride/oxide interpoly dielectric. When the control-gate voltage ( $V_{\textrm {CG}}$ ) of a selected cell in the erased state is 5 V, the electrons in the FG are captured in the traps, because the trap energy level ( $E_{T}$ ) is lower than the Fermi energy level ( $E_{F}$ ) of the FG ( $E_{T}- E_{F} ), which leads to the increase in $I_{\textrm {BL}}$ . When the $V_{\textrm {CG}}$ of the selected cell is $V_{\textrm {th}}$ , trapped electrons are emitted to the FG, because the $E_{T}$ is higher than the $E_{F}$ of the FG ( $E_{T}- E_{F}>0$ ), which leads to the decrease in $I_{\textrm {BL}}$ .