Effect of wafer position in ingot on the light and elevated temperature induced degradation (LeTID) of multicrystalline silicon

Light and elevated temperature induced degradation (LeTID) of high-performance (HP) multicrystalline silicon (mc-Si) is a problem which affects manufacturers of mc-Si PERC cells and its root cause is still being debated. Several hypotheses for the root cause have been suggested which involve metal precipitates, and/or the introduction of hydrogen. Some of these hypotheses may be tested by controlled LeTID experiments in different parts of the mc-Si ingot, which are known to have different grain sizes, dislocation densities, doping and a large change in some of the impurities present. Limited publications are available showing the LeTID behavior of mc-Si in different parts of the ingot. In this study we show that the degradation rate and extent of LeTID during accelerated processing is not majorly influenced by the wafer’s origin within the ingot which is studied here. We also confirm that the firing temperature before the degradation process has a large impact on the degradation extent, and this relationship is not significantly affected by the wafer’s origin in the ingot, either.