A flexible hardware architecture for real-time airborne wavenumber domain SAR processing

This paper presents the design of a compact real-time SAR hardware architecture for small unmanned aerial vehicles (UAVs). The architecture is flexible for a variety of SAR algorithms whereby the focus of this paper is on the wavenumber domain (ω-k) algorithm. Characteristics of the RISC/FPGA based hardware architecture are real-time processing for sensor data rates of 300 Mbit/s with image dimensions of 8k × 4k pixel, implemented on a 233 × 160 mm printed circuit board with a total power dissipation below 15 W.