FPGA based effecient architecture for conversion of binay to residue number system

Today the most interesting research topic in theoretical point of view is Residue Number System (RNS). Its significance originates from the lack of carry propagation between its arithmetic units. To implement any modular process, the important step is the conversion from a residue number system (RNS) to binary. In modern telecommunication system and multimedia applications, the use of RNS increases day by day due to its many advantages such as low power consumption, high speed, very precise etc. Usually the translation of the output from residue to binary is the vital point in successful realizations of application specific architectures based on residual arithmetic. In this paper a novel architecture of parallel forward conversion (Residue to Binary number system) for signed number has been proposed successfully. This article also highlighted the mapping of this projected architecture on FPGA and shown it is very efficient on FPGA technology.