Strain distribution analysis in Si/SiGe line structures for CMOS technology using Raman spectroscopy

Strained silicon underneath the field-effect transistor gate increases significantly the charge carrier mobility and thus improves the performance of leading-edge Complementary Metal Oxide Semiconductor (CMOS) devices. For better understanding of the structure-strain relationship on the nanoscale and for optimization of device structures, the measurement of the local strain state has become essential. Raman spectroscopy is used in the present investigation to analyze the strain distribution in and close to silicon/embedded silicon-germanium (SiGe) line structures in conjunction with strain modeling applying finite element analysis. Both experimental results and modeling indicate the impact of geometry on the stress state. An increase of compressive stress within the Si lines is obtained for increasing SiGe line widths and decreasing Si line widths. The stress state within the Si lines is shown to be a mixed one deviating from a pure uniaxial state. Underneath the SiGe cavities, the presence of a tensile stress was observed. To investigate a procedure to scale down the spatial resolution of the Raman measurements, tip-enhanced Raman scattering experiments have been performed on free-standing SiGe lines with 100nm line width and line distance. The results show superior resolution and strain information not attainable in conventional Raman scans.