A reconfigurable data-flow architecture for a class of image processing applications

This paper aims to device an architecture which uses the capability of asynchronous concurrency of the data flow architecture as well as spatial parallelism of SIMD machines for a class of image processing applications using reconfigurable processing elements (RPE). Overall processing speed is enhanced by: (a) concurrent functioning of the RPE; and (b) replacing software execution of signal processing functions by hardware approach using FPGA as RPE. Thus, a hybrid architecture, which functions as a data flow machine at a functional level and exploits the capability of spatial parallelism by incorporating modified SIMD concepts is presented.