Full coverage manufacturing testing for SRAM-based FPGA

Full coverage detection of faults is required for FPGA manufacturing testing. Many researches for FPGA test only focus on algorithms of reduction configuration numbers for a configurable logic blocks (CLB), or interconnect routings without application for manufacturing testing. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, SOC co-verification technology based in-house FPGA functional test environment embedded with an in-house computerized tool, ConPlacement, can detect CLBs and interconnect routing of FPGA automatically, exhaustively and repeatedly. The approach to implement full coverage detection of CLB and interconnect routing faults by the FPGA functional test environment is presented in the paper. Experimental results of XC4010E demonstrate that 17 configurations are required to achieve 100% coverage for a FPGA-under-test.