From real-time emulation to ASIC integration for image processing applications

A methodology for deriving image processing ASICs from the results of their real-time emulation on the Data-Flow Functional Computer is presented. The aim of the method is to reduce the time and effort required for synthesizing and validating ASICs after emulation. This is achieved by optimizing the architecture validated on the emulator and integrating the optimized resources. The results of the derivation of a defect detector are presented.