Transmission Line Pulse Test Method for Estimating SEB Performance of $n$ -Channel Lateral DMOS Power Transistors

A novel wafer-level method is described for predicting lateral-diffused MOS transistor single-event burnout (SEB) levels to assist device engineers in the development phase of radiation-hardened power transistors. The method uses a transmission-line pulse (TLP) tester together with scribe-line transistor test structures. Technology computer-aided design (TCAD) is used to estimate static $I_{d} - V_{\mathrm {dss}}$ behavior and device transient response to heavy ion strikes. Various comparisons are made between TCAD, TLP measurements, and heavy ion testing. TCAD simulations provide physical justification for using TLP measurements to estimate SEB.