A Hybrid Implant Doping Technique with Plasma Immersion Ion Implant (PIII) Process for 10 nm Fin Cannel of 3D-FET

In this work, a sub-10 nm high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices with symmetrical N/PMOS characteristic were fabricated by a new hybrid dopant technology of plasma immersion ion implant (PIII) with traditional ion implant. This method was demonstrated to effectively reduce contact resistance and increase driving current of 18% in FinFET device. A remarkable improvement of sub-threshold swing (24%) and DIBL (36%) were also reported in this work. A low resistance of TiSi silicide process are incorporated in our FinFET platform to achieve a higher Ion / Ioff current ratio of 106 . The whole device fabrication can be fully integrated in CMOS device.