3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via

A low-cost power supply technique for a 3D system-on-a-chip (SoC) is experimentally confirmed by using highly doped silicon via (HDSV). A 100 × 100 μm2 HDSV in a 2 μm thick silicon wafer exhibits a resistance of 2.7 Ω after wafer thinning, bonding, and annealing. A 9-stack 3D SoC is designed with an HDSV power supply, and its area overhead is calculated as 11%. Moreover, technology computer-aided design simulations show that the resistance of the same HDSV could be as low as 22 mΩ, which turns into an area overhead of 0.09%. This work shows detailed experimental results of wafer bonding and current–voltage (IV) characteristics and discusses the applied 3D SoC design.