Correcting image placement errors using registration control (RegC) technology

The 2009 ITRS update specifies wafer overlay control as one of the major tasks for the sub 40 nm nodes. Wafer overlay is strongly dependent on mask image placement error (registration errors or Reg errors) 1 in addition to CD control and defect control. The specs for registration or mask placement accuracy are twice as difficult in some of the double patterning techniques (DPT). This puts a heavy challenge on mask manufacturers (mask shops) to comply with advanced node registration specifications. Registration test masks as well as production masks were measured on a standard registration tool and the registration error was calculated and plotted. A specially developed algorithm was used to compute a correction lateral strain field that would minimize the registration error. A laser based prototype RegC TM tool was used to generate a strain field which corrected for the pre measured registration errors. Finally the post registration error map was measured. The resulting residual registration error field with and without scale and orthogonal errors removed was calculated. In this paper we present first results of registration control experiments using the prototype RegC TM tool.