Challenges and solutions for 14nm FinFET etching

The gate for FinFET structure is graved into a 3D architecture just as a fin fork so that we can control device on/off through the surfaces of its top and two sides. Such design can greatly improve the controllability of circuit and reduce leakage and shorten gate length. Although FinFET has so many advantages, such as lower power, smaller size and etc., it brings big challenges to process, especially to etching process. This paper will analyze the main challenges and solutions for 14nm FinFET etching, including intracell depth loading, profile and angle control of Fin/STI/Gate, Spacer etching, residue control, CD loading and CD uniformity control.