Observation of Tunneling FET Operation in MOSFET with NiSi/Si Schottky Source/Channel Interface

Introduction As the MOSFET scaling goes down to 10nm region the supply voltage (Vdd) should be decreased accordingly. However, Subthreshold (S) slope cannot be scaled down below 60mV/decade at Room temperature (RT) and this fact hinders the Vdd scaling. The tunnel FET is one of the promising candidates to decrease S [1]. Schottky barrier tunneling FET (SBTT) has many advantages to ordinary PN junction tunnel FETs: low parasitic resistance, better short channel effect immunity and high controllability of output characteristics by the silicide material selection [2]. We fabricated tunnel MOSFETs with NiSi/Si Schottky barrier at the source/channel interface. This work is to find the tunneling emission, S slope dependence on temperature revealed that thermionic emission over the Schottky barrier dominated at temperatures higher than 150K. However, tunneling through the Schottky barrier became dominant at lower temperatures. Experiments Figure 1 shows the Schottky MOSFET structure fabricated on SOI substrate with Si thickness of ~55nm. The Si layer is p-type (1x10cm). The BOX-layer thickness was about 125nm. The source/drain region was fully silicided by 12-nm thick Ni deposition followed by 400C 30 sec silicidation annealing, and the excess Ni layer was chemically etched. The overlap of NiSi/Si interface under the gate electrode, which is indispensable for the tunnel FET operation, was formed by the encroachment phenomenon of NiSi during the silicidation [3]. The gate insulator was SiO2 with the thickness of 60 nm.