Challenges of back end of the line for sub 65 nm generation

This paper presents a review of interconnect challenges for sub 65 nm node. From this generation, porous ultra low K (ULK) dielectric materials (dielectric constant k < 2.1) are required. Their porosity makes integration very difficult, due to the mechanical weakness and process interaction issues (especially during stripping, CVD metal barrier deposition...). To overcome these process incompatibilities and keep the 'effective dielectric constant' low, dual damascene architecture becomes more and more complex and requires additional steps (porosity sealing treatment, degas steps, supercritical CO2 clean, low k dielectric barrier, self aligned barrier...). Possible contamination trapped in the porosity (moisture, metallic residues...), and lower thermo-mechanical properties of ULK will probably impede reliability. Copper resistivity increase with dimension shrinkage will also be an extra issue.