Selective process aware OPC for memory device

Many issues need to be overcome in creating a production-worthy sub-k1 (<0.25) process. The repeating photo-etch sequential method for clear and dark mask type is susceptible to overlay issues while accuracy of first pattern is critical for the space technology. Both technologies require improved model accuracy and process margin. Because of this, even traditionally noncritical regions of a layout may contain process margin-limiting defects for double patterning technology. An integrated OPC-Verification-Selective OPC procedure is developed to improve quality of results for non-critical regions while retaining fast TAT. The first step utilizes a fast OPC method with reduced TAT. Next, a lithographic verification tool is used to perform a thorough check of the OPC results, including process window analysis. This determines which points limit process margin. Finally, advanced OPC methods are applied to reprocess the areas limiting process margin. These advanced OPC techniques may include broader lithographic analysis, field-based correction and process window consideration. Since advanced OPC methods are only applied to part of the design, TAT is fast. TAT can be further improved by treating critical regions differently. Critical regions will not be processed in the initial OPC or intermediate verification steps, but will be corrected by the advanced OPC methods. This methodology is called Incremental OPC as it applies the most appropriate OPC techniques to each area of the design. As a result, process margin limiting defects, side-lobe printing and subresolution assist feature printing can be eliminated prior to mask tape-out with minimal impact to TAT. In this paper, Incremental OPC is compared to "all-or-nothing" OPC techniques which must be applied across an entire pattern.