Memory device with seperated capacitor

It is provided to the memory device having a separate arrangement of the capacitor. The memory device is implemented as a multi-chip packages to which the first die and the second die stacking. The first die is a memory die including a first capacitor connected between the first circuit and a first power supply voltage and a first ground voltage is connected to the memory cell array is driven in the first power supply voltage and a first ground voltage have. The second die may be a capacitor which is stacked die to the first die through the through-electrode and a second capacitor that is connected in parallel with the first capacitor of the first die. A memory device may be a constant power supply voltage, without the chip area increase of the second die of the capacitors and by the parallel connected memory devices connected via the first circuit through electrode a capacitor connected to a power supply voltage and the ground voltage for driving the first die it can be supplied stably.