Timing control circuit for Josephson IK RAM

Toward realization of a fully decoded random access memory (RAM) with Josephson devices, a method of designing and constructing the important timing control circuit employing dc-powered loop logic is described. In order to obtain high speed and stable read/write operation, an on-chip timing control circuit for the nondestructive RAMs including decoder, XY-driver and readout data-bus employing loop logic is investigated. Positive and negative transition-edge-triggered single-shot pulse generators (POS, NOS) are newly designed for generating the timing signal pulses and the latter are appropriately delayed using the current steering time, thereby providing a very simple, fast and stable timing control circuit. the timing control circuit for a 1K RAM employing 5-μm Pb-alloy technology was designed and proper operation confirmed by an experimental read access time of 3.3 ns.