Chapter 5 Functional Nanoscale Devices

The recent emergence of fabrication tools and techniques capable of constructing structures with dimensions ranging from 0.1 to 50 nm (see Fig. 5.1) has opened up numerous possibilities for investigating new devices in a size domain heretofore inaccessible to experimental researchers. The WTEC nanotechnology panel reviewed research in the United States, Japan, Taiwan, and Europe to find that there is considerable nanoscience and technology activity in university, industrial, and government laboratories around the world. The insight gained from this survey suggests areas of strength and areas of possible improvement in the field. There is intense study around the world to determine the exact point in dimensional scaling where it becomes either physically unfeasible or financially impractical to continue the trend towards reducing the size while increasing the complexity of silicon chips. In some of the same laboratories where research activities on Si are decreasing, research activities on singleelectron devices (SEDs) are increasing. Although there are myriad questions involving electrical contacts, interconnections, reliability, and the like, one of the fundamental issues in the miniaturization/complexity debate concerns the Si MOSFET itself when the gate length is reduced to less than 50 nm. Does it behave like a long gate device or does the output conductance increase to impractical levels due to short-channel effects? Based on the WTEC panel's survey, most of the activities examining these questions are taking place in Japanese industrial laboratories.