Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

Fully-scaled-down, 65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nm/sup /spl phi//-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDI via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDI with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDIs with k/sub eff/ /spl sim/3.0 is applicable especially for the 65nm-node, low-power ASICs.