Process for the preparation of a thick isolation collar with reduced length

The present invention relates to a grave capacitor memory cell structure with a vertical collar portion, the leakage currents from an adjacent vertical parasitic transistor, which is located between a vertical MOSFET and an underlying grave capacitor can be suppressed. The vertical insulation collar having a width of about 0.50 microns or less, comprises a first portion, which is partially outside of the trench, and a second section that is within the trench. The first portion of the collar oxide is thicker than the second oxide portion, whereby parasitic leakage currents are reduced.