Tackling Fundamental Challenges of Carrier Transport and Device Variability in Advanced SinFinFETs for 7nm Node and Beyond

We demonstrated that the fundamental scaling challenges of carrier transport and device variability can be tackled by S/D epitaxy and HK/MG RPG optimizations on the leading-edge 7nm Si $n$ FinFETs, paving the way for continuous scaling. Mitigations of S/D long-range Coulomb interactions and gate-corner work-function roll-up enhance $I_{\text{DSAT}}$ by 18% and 9% respectively at constant gate overdrive, translating to a 13% speed-power enhancement in the ring oscillator. These techniques show larger $I_{\text{DSAT}}$ enhancements than that of $I_{\text{DLIN}}$ . By using an improved characterization method, their unique transport characteristics are clarified.