Three-step search motion estimation chip for MPEG-2 applications

In this paper, a hardware implementation of a 9-PE architecture for three-step search block-matching motion estimation algorithm is proposed. With intelligent data arrangement and memory configuration, the proposed architecture can reach the requirements of low costs, high speed, and low memory bandwidth. With 0.8 micrometer CMOS technology, the proposed chip requires a die size of 6.90 by 5.98 mm and is able to operate at a clock rate more than 50 MHz.