High Speed, Area and Power Efficient 32-bit Vedic Multipliers

This paper presents two novel Vedic-multiplier architectures which follow the technique of concatenation and rearrangement of partial products. These architectures exhibit their excellence in speed, area, and power. Thus resulting in energy-efficient operation and improved Energy-Area product. The first design is Ripple carry adder based partial product concatenation (RCA_PPC) and achieves this goal through rearrangement of partial products. The second proposed design is Carry Save Adder based partial product concatenation (CSA_PPC) with another block which called add-by-constant block in this work. Both of these exhibit competitive results in comparison with the existing Vedic-multiplier architectures in terms of area and power. The RCA_PPC architecture shows advantages of high-speed, Energy-efficient, and improvement in Energy-Area product over other architectures discussed in this paper. The CSA_PPC architecture shows an advantage of improvement Energy-Area product when compared to the existing architectures. Simulation results specify that these proposed architectures are Energy-Area efficient as there is a significant decrease in area, power and time delay.