On Small Signal Frequency Stability under Virtual Inertia and the Role of PLLs

This paper presents a methodology that aims at identifying virtual inertia (VI) gain limitations from virtual synchronous generators (VSGs) while maintaining the frequency stability considering the delay associated with the frequency measurement process. The phase-locked loop (PLL) is typically used for frequency estimation that is used to calculate the rate of change of frequency (RoCoF) and it drives the VI loop. The PLL is generally accompanied by a low-pass filter that aims to suppress the impact of harmonics. This filter introduces a delay that when used with the VI control loop causes stability issues for high values of VI gain. A comparison of various PLL approaches suggests that certain variants tend to permit higher value of cut-off frequencies which can be utilized to increase the VI gain limit from VSG. This study presents a method by which the upper limit on VI gain can be quantified and related to the cut-off frequency of the PLL low pass filter that is indirectly representing the delay. It is performed using small signal frequency stability analysis on the frequency domain model of the grid with virtual inertia emulating VSG. The effective maximum VI gain from VSG is explored while satisfying the frequency measurement accuracy specification considering harmonics. The results show that the requirements of reaching a stable operation with sufficient stability margins can still be met with a faster PLL-based system and the potential increases in VI support from VSG can be quantified using the proposed method. The study has been first performed on a single machine single inverter bus (SMSIB) system and is generalized to the multi-machine and multi-inverter system.