Energy efficient and low noise OTA with improved NEF for neural recording applications

Analogue front end (AFE) design plays a prominent role to specify the overall performance of neural recording systems. In this paper, we present a power efficient low noise operational transconductance amplifier (OTA) which is power consumable block for multi channel neural recording system with shared structure. Inversion coefficient (IC) methodology is used to size the transistors. This work focuses on the neural recording applications which show > 40 dB and up to 7.2 kHz bandwidth. The proposed architecture, which is referred as partial sharing operational transconductance amplifier with source degeneration, results in reduced noise, hence improving NEF. Simulation results are carried in UMC 0.18 μm and shows improved gain of 66 dB, phase margin of 94°, input-referred voltage noise 0.6 μV/sqrt(Hz) and power consumption of 2.15 μW with supply of 1.8 V.