A Thermoelectric Energy Generator with Double Cavity Design by Single Polysilicon Layer in Standard CMOS Process

The performance of a thermoelectric energy generator (TEG) can be improved by having thermocouple materials with higher Seebeck coefficient, thermocouple configuration with better thermal isolation, and thin-film layer deposition/etching with effective electrical insulation. A TEG design by the 1P6M (1 polysilicon layer and 6 metal layers) standard CMOS process in semiconductor foundry service (TSMC) is proposed in this work to achieve better energy harvesting performance. The in-plane thermocouple has higher Seebeck effect by the single polysilicon layer at different doping rates. The TEG configuration is with double cavity design to seal the thermocouples above-and-below for better thermal isolation, and the deposition layers are in mask-less design for better electrical insulation. Measurement results of a $5\times5$ mm2 TEG chip show that higher thermoelectric conversion, better thermal isolation and electrical insulation can be realized. The voltage factor 15.604 V/cm2K and power factor $0.105~\mu \text{W}$ /cm2K2 are about $5.40\times $ and $2.34\times $ , respectively, of those of the previous work by the CMOS process with two polysilicon layers. This design, implementation, and experiment have achieved the best performance in all TEGs by CMOS process in semiconductor foundry.