Design and automatic generation of area-efficient ring oscillator based addressable test chips

Ring oscillator has been frequently utilized to extract circuits' AC parameters and analyze their variation properties nowadays. Addressable test chip has been introduced to integrate more test structures on one chip without losing the testing accuracy, yet layout work of test chip containing large numbers of test structures is time consuming and prone to manual errors, which becomes even worse for complex test structures such as ring oscillators consisting of amounts of basic cells. In this paper, an area-efficient ring oscillator based addressable test chip design is proposed along with a dedicated automatic layout generation procedure. Special attentions are paid to the schematic and layout design, and the experimental results of the implementations at both 16nm FinFET and 28nm technology nodes are obtained and analyzed to further confirm its feasibility and reliability.