ADP efficient 4-level DWPT using approximation

Abstract In this paper, presented an efficient 4-level discrete wavelet packet transform (DWPT) using approximation where area and delay are considerably reduced. It gives lesser number of hardware arithmetic computations and lesser delay required at each computation level. Compared with the existing design, the presented design gives 16.34% less area for block size 2. The Area Delay Product (ADP) of proposed shift add register approximated design have saving of 21.7% and CPD of 4.4% lesser for block size 2 over existing design.