A Simple Approach to Optimizing Ultra-thin SiON Gate Dielectrics Independently for n- and p-MOSFETs

A technique for optimizing ultra-thin (EOT ~ 1.1-1.3 nm) SiON gate dielectrics independently for n- and p-MOSFETs is demonstrated. Selective nitrogen-enrichment for the nMOS and fluorine incorporation to the pMOS regions were both performed by ion implantation into the Si-substrate with resist masks before gate oxidation. The former provided suppression of gate leakage current and enhancement of drain current to nMOSFETs. The latter improved the NBTI of pMOSFETs without enhancing the B penetration. Moreover, the incorporation of F was found to be a quite useful tool for lowering |Vth| in pMOSFETs. The incorporation of F was shown to bring down pMOS |Vth| by more than 150 mV without any degradation in hole mobility or short channel effect immunity. Since pMOSFETs with N-rich SiON gate dielectrics, as well as high-k pMOS, suffer from excessively high |Vth|, this finding is quite important. In fact, by applying the F-incorporation technique to 65-nm devices, significant Ion enhancement (~8%) was successfully achieved for high Ioff conditions. This technique is considered operative also for pMOSFETs with high-k gate dielectrics and/or metal gate electrodes