Modeling of Stress Induced Layout Effect on Electrical Characteristics of Advanced MOSFETs

Layout dependent stress induced effects on current drivability of 90nm node CMOS devices have been modeled by both performing stress modeling in process simulation and device simulation with stress dependent mobility model. It has been demonstrated that dependence of drive current of both n- and p-MOSFETs on source/drain size is successfully modeled. In addition, with this procedure, the performance improvement with stress engineering such as modifying shallow trench isolation (STI) process and using nitride liner deposition on gate electrodes can be well reproduced.