Control gate etching method

The present invention provides a method for controlling the gate etching, the method comprising: providing a flash memory cell region of the structure; a photolithography process and an etching process so that an opening is formed in the mask layer; in the mask layer etching said polysilicon as a mask control gate, so that the polysilicon etch stop on the interlayer dielectric layer, located between the retention layer on the polysilicon the STI dielectric; over-etching of the polysilicon control gate; for the interlayer dielectric layer polysilicon etching process step of the first step; interlayer dielectric layer on said polysilicon etching process step of the second step, removing the inter-layer polysilicon floating gate layer, the dielectric sidewall spacer; of the spacer layer is etched floating gate. By the method of the present invention to the prior art inter-polysilicon dielectric layer etching step in two steps, using isotropic etching gas as the etching gas in the process, shallow trench isolation can improve the loss of the semiconductor device to ensure performance and reliability.